In my not so humble opinion, one could write a doctorate thesis on the mistakes Intel has made in design and execution of it's PC products over the past 6 years. With today's announcement that Intel is canceling "White powder up Hotellini's nose" and "Tuck it up your butt Willy", you know the fools on the hill have no clue. As anyone in the IT industry knows, Intel does not respond well to competition let alone superior products by the competition. Intel has made one blunder after the other since AMD launched Athlon years ago. Intel has had repeated defective products, canceled products, delayed products, missed delivery dates, factory closings, chipset shortages requiring them to buy ATI chipsets, etc. The list of BLUNDERS by Intel is almost endless and continues as I write.
Having a marginal 65 nano process at best, which actually just about competes on power consumption with AMD's 90 nano process, shows quite clearly that Intel is WAY behind the eightball despite the media hype! As history has shown, despite the years of denial, the P4 was a defective design rushed to market to try and kill Athlon, which it never accomplished. Now with Intel's most recent chip "delays" which will turn to cancellations next year, you will see some more cobbled crap from Intel that only losers would even consider buying.
So once again just as with their 90 nano process, that was according to Intel: "ahead of their development schedule", and then showed up in the marketplace over a year LATE and it was STILL a defective design as released with massive voltage leakage that required special cooling, cases, etc. Intel's 65 nano process hasn't even allowed them to catch up to AMD's existing products. It's all just hype and no substance, as usual for Intel.
What we have is Intel's PR machine spinning overtime as usual and no competitive products ANYWHERE in Intel's product line. They even lost their minimal advantage with the Pentium M in the laptop segment as the 25W and 35W Turions have stolen Intel's lunch. Bottom line is only a fool would buy any Intel product in the foreseeable future when AMD's products, by virtually all industry standards and reports, are far, far superior. It's encouraging to see consumers voting with their wallets. At least some consumers and industry sources have seen thru Intel's deception and purchased AMD products. Intel's days of extortion are pretty much over now that the cat is outta the bag.
Beenthere, how is having bad processor equate to having bad process technology??? Are most people that uninformed and stupid??? If Intel introduced Dothan for their first 90nm part, then people would have been praising Intel's 90nm process. Intel rather put Prescott out first, so people thought badly about it. If you DO read about what happened, focus has been all shifted to Merom/Conroe, OUT OF CEDARMILL/PRESLER PROJECTS. What happens then?? All the speedpath optimizations and low power optimizations that are supposed to go to Cedarmill/Presler went to Merom/Conroe. Merom will be ~30W DESPITE the fact its dual core, 4-wide architecture. Does Pentium M have low power compared to Prescott because its on a better process technology??? No.
Intel has one of the best 90nm process, if not THE best.
It's nice to see this will be a decent enthusiast chip.. Guys should get 1500-2000Mhz overclocks which will put some excitment into to the overclocking scene again. Sure stock they will suck but people I know don't run that way. A 4.5Ghz Cedar is fast no doubt about it probably equates to a 3Ghz A64 in a round table of benchmarks. As it happens 3Ghz seems pretty normal these days especially with the new Opteron 939's. So it would be great to hold a "overclockers shootout" of some sort when you guys have time. Say a 144 Opteron vs. Pentium 631 :D
One small error PP: 2 "Presler is physically two separate dice on a shared package,"
Bascially, one can tell from the memo that the FX-60 will probably be dual core 2.8 GHz CPU (increments of 5 instead of two now to match Opteron plus two cores means +5 instead of +2) and there will be a dual core 2.6 GHz called 5000+. All of the single core Athlon 64s will be reduced in price to be below all the dual cores (except the 4000+ will be a little above the x2 3800+). All the semprons will be below single core athlons except the 3400+ sempron will be a bit above the 3000+.
Have fun dreaming of what you are going to buy. From the looks of things, AMD will be phasing out single core high speed processors sooner than we think. That means no 3.0 GHz in '06 Q1. :(
Uhhh... I think the FX-60 is actually a 3.0GHz DDR2-667 single core part. Looks like the FX-59 3.0GHz DDR-400 got shelved, presumably to avoid confusion having two at the same clock speed but different memory.
X2 5000+ ought to be 2.667GHz dual core on DDR2-667.
Not your fault, but I don't believe they have the details correct on that site. In fact, I'm almost sure of it.
333 MHz CPU bus speed seems questionable at best to me. We might get that, but right now even the best 939 motherboards get flaky above 300 MHz CPU bus, and DDR2 isn't going to fix that. I'm inclined to think that AMD would go with a 266 bus instead, but really I don't think they'll even do that.
Why? Simple: RAM speed on AMD systems is really independent of CPU bus speed. So, you can have a 200 MHz CPU bus with 1000 MHz HyperTransport, and the RAM can run at anything you want! (The RAM speed is derived from the CPU speed and has nothing to do with the CPU bus speed.) The 1000 MHz HT bus listed leads me to believe AMD will stick with a 200 MHz base CPU bus speed and 5X HT multiplier. The only change will be that instead of a CPU/12 divider on the 2.4 GHz chip, they'd have a CPU/8 divider. (That would actually result in DDR2-600, but since CPU/7 would give DDR2-686, they'll have to stick to the lower speed.)
Given that information, my guess is that the X2 5000+ will actually be the same as the X2 4800+, only with DDR2-667 support on socket M2. In other words, my bet right now is that M2 5000+ will be 2.4 GHz. It makes sense: the socket shift will almost certainly come with a speed increase, and so AMD will have different model numbers for the new sockets. It will basically be like the past: 2.2 GHz 754 is a 3200+ while the 2.2 GHz 939 is a 3500+.
I agree with Jared about the FSB. The FSB is not the same on the Athlon 64's as the Athlon XP's and the Pentium 4's, Stephenbrooks. You can't just go to 333 MHz to match the ddr2 memory speeds. The FSB if you can even call it that will always be a HT bus running in half or full duplex mode and will probably stay a multiple of 200 for awhile. Just my guess.
But I disagree with Jared about what the chips are in the leaked pricing memo. If it is a true memo, then I think all processors on it are Socket 939 (no DDR2). It says Q1 '06 and I think the new sockets from AMD are not due until March. We are seeing the last of the Socket 939 processors and I think they are trying to move to all dual core similar to intel. Dual core on the FX processor (2.8 GHz giving 5 increment model numbers like the opterons) and a 200 MHz bump on the X2 5000+ to 2.6 GHz. We were all expecting a 2.6 GHz dual core part but a 2.8 GHz is a little iffy without the 65 nm shrink to keep things consuming less power.
Oh, I didn't look at the AV link, mlitt, so I wasn't referring to that information. I'm still wondering what the 5000+ will be. If you look at the clock speeds and past performance, Toledo at 2.6 GHz is almost certainly a 5200+, while Manchester at 2.6 GHz would be the 5000+.
I'd guess we'll see a couple 2.6 GHz socket 939 X2 chips in early 2006. I could be wrong on the socket shift and AMD will just use the same names for the same speed, but the 754 to 939 shift indicates that they like to take advantage of faster platform performance by increasing the model number, so I really don't think they'll do that. If M2 chips are 5% faster than 939 chips, there's no way the marketing department will let that pass by without some hype. :) Besides...
4800 * 1.05 = 5040
4600 * 1.05 = 4830
If the 5% guess is correct, I expect a 200 point model number change. Though it would be nice if they actually didn't overlap numbers, so in the above two instances they could call the 2.4 GHz 512K/1MB M2 chips the 5050+ and 4850+. Wouldn't it be great to actually have less obfuscated performance for once?
I really appreciate this article. Curious as to how you secured these chips without having to sign an NDA.
AMD's A64s need to be able to reach 3.0 GHz in order for them to stay competitive with these new 65nm intel chips on the overclocking front. While some of their venice chips are definitely reaching those speeds, especially with a decent voltage bump, most don't quite make it. I expect that by the time these 65nm chips come out though, a 3.0 GHz OC on a 3800+ dual core system should be the norm. Competition is good, now we just need intel to lower their price on their motherboards and not attempt to restrict OCing on their motherboards chipsets.
I didnt see anything about (real) stability and throttling.
POV-Ray is all nice and such, but does it put as much stress on the core(s) as, let's say, S&M 1.7.3?
Also, I havent seen any temperatures. :)
Granted, it's just a preview, but still. I'm mostly interested in throttling. 4.5GHz on CPU-Z is cool, but does it deliver that when you heat up the kitchen?
Is Intel back in the high performance section ? Can they finally defeat AMD in gaming benchmark ? What does AMD in store for us ? Do you guys think that Intel are going to pawn AMD ? : ( Question ... Anyways this is a good sign of competition from Intel and i am know interested in getting a Intel 65nm if they perform good and be very competitive in gaming benchmark.
65nm P4s are only a temporary thing. They sued the 65nm to gain benefits inmaking a cheaper product, while getting better in the performance/watt issue and getting the P4 into acceptable powerlevels and heatlevels.
However..Intel gives a damn about 4Ghz P4 etc for one reason. Conroe will burrow P4 in week 36 2006. And Yonah will take a huge part aswell until Conroe/Merom. Netburst is dead, all hail Pentium-M and it´s successor.
I found it very interesting that Intel actually put two seperate cores and dies on the new dual core chip. This is very interesting as it affects pricing but decreasing cost (of defective dies) thus places this processor in a possibly lower pricing point than AMD's. And if you like heavy encoding where netburst has always done well in, this chip could be your best bet, espeically if the increase in cache increases the benchmarks like the P4 notably has with such. IMHO
quote: This is very interesting as it affects pricing but decreasing cost (of defective dies) thus places this processor in a possibly lower pricing point than AMD's
It does indeed increase yield (thus decreasing cost), however we have no way of knowing how good the original yield is, so they may still be more expensive to produce.
It also decreases performance by increasing the latency between cores and increasing the bandwidth requirements of the FSB...
I have to say that I'm a little skeptical on the whole core-to-core bandwidth topic. I think there's a lot less inter-core communication than some people think. The FSB latency and bandwidth is the bigger question, so really I doubt that having split cores (Presler) is any worse than Smithfield - the extra cache probably more than compensates.
Of course, X2 still has the latency advantage (by a huge margin), but I'm only looking at the Intel side here. I mean, we can't really draw any conclusions from Presler vs. Toledo other than to (most likely) say that Toledo is faster. Why it's faster is almost certainly due more to the overall architecture and design than the faster inter-core communication.
It will be interesting to see if Intel can get latencies down with future chips without resorting to an integrated memory controller. I believe at present Intel's best is around 100ns latency for RAM while AMD is 30 to 40ns. If Intel could even get their chips to 75ns, it would be a huge improvement.
Fair enough Jarred...but we can probably get a good idea of the core to core advantages by comparing a dual core Opteron to a 2P Opteron rig at the same speeds...
As to Presler v Smithfield, maybe I'm confused but isn't Smithfield a split core as well? Any corrections greatly appreciated!
Heh - from this article by Anand, I gathered that Smithfield wasn't split and Presler is. Needless to say, I haven't personally pried off the heat spreader on my Smithy, so I don't know for sure. :) (I'm also open to enlightenment if someone has definite evidence - I'm being too lazy to research it right now!)
2P Opteron vs. DC Opteron isn't quite the same as split core vs. single core, though. The difference between communications sent over the FSB, through the chipset, and to a separate socket is going to be quite a bit larger than simply splitting the cores. I'm sure a unified core has faster inter-core communication speeds, but the question is: how fast do they need to be?
If such signaling only occurs on rare occasions, the real world performance difference between split cores and unified cores (of dual-core packages) may be less than 1 or 2 percent in real-world testing. There's also the question of 2P vs. DC on Intel in contrast to the same on AMD. Intel tends to have more bus bandwidth and lower latency, and perhaps better RAM prefetch logic as well. Opteron DC might be 5 to 10% faster while Intel would only be 2% faster, or maybe it's the reverse of that. (Again, I'm being lazy.)
Basically, since the architectures of NetBurst and K8 are vastly different, DC/SMP/etc. can benefit - or not - from technologies to varying degrees. And yes, I realize for many that's going to be a "duh!" statement. "Hey people - bananas are very different from oranges!" Shock and awe.... Still, it bears mention since we still have people out there that don't understand that pipeline stages, architectural designs, etc. are at least as important as raw clock speeds.
Core-to-core is extremely important in a lot of multi-threaded applications. Remember that the programming model for threading is that multiple threads share one address space and so have shared access to data. Thread synchronization with mutexes and such requires that all processors have fast access to the mutex variables. As such, core-to-core communication is crucial.
Thanks highland...some other questions if you could help.
Do you have any idea as to how much bandwidth would increase for just the core to core traffic during multitasking?
What effect would increased latency for the core to core have on overall multitasking?
I should also mention that DC could actually be slower than 2P in cases where you have say 2 DIMMs per socket and a UMA-aware OS.
Here's the real problem, Highland: in theory faster core-to-core speeds are important for SMP code. In reality, mutex and thread synchronization is bad. You don't want SMP software to spend a lot of time waiting to enter exclusive code blocks. In an ideal SMP application, you spend a fraction of time splitting up a task into two equal halves, then you let two cores churn away on those tasks for a relatively long time, and then you spend a fraction of time combining the results/synchronizing. If you're spending a lot of effort on thread synchronization, then you've got a task or algorithm that doesn't work very well for SMP in the first place.
This is more guesswork and supposition than actual knowledge. If someone has a concrete set of benchmarks that show real-world SMP doing much better (or worse!) on DC vs. 2P, I'd love to hear about it. If you can prove that the faster core-to-core speeds are what leads to better results in a real scenario, I'd like to hear about the application as well. Maybe I'm just not being creative enough, but I'm having a difficult time coming up with a task that's going to do great on SMP and also show a marked improvement on DC vs. 2P. The more independent the pieces of a task are, the better it will do on SMP setups, and conversely the less important core-to-core signaling becomes.
Yes, "an ideal SMP application" may allow coarse grained division of labor. That may apply to supercomputing applications, where array/vector operations tend to dominate. That's a good model of SIMD computing, but that isn't the only model that users will run into.
I think that class of problem is actually pretty rare. More often you need concurrent access to shared data. E.g., a web server with lots of front-end tasks talking to a multi-threaded database server. Since any number of threads may be writing new data while other threads are querying for data, all data accesses must be synchronized. For this class of problem, I expect the AMD design will have a noticable advantage.
This is significant, because I believe this class of problem is far more relevant in every day use. Think of the filesystem drivers in your OS, the databases behind big search engines like Google, etc., they're all about moderating multiple accessors to shared data. The faster your core-to-core communication, the better you can handle this type of task, and you run into this task every minute that you touch a computer.
There will be a few areas it helps, but I really don't think it will matter much. Most mutex accesses will be a very small fraction of the total compute time. Let's say that in a given second, you have 2 billion operations that a CPU can execute. How many of those will have to do with core-to-core work? If I were to take a stab at a figure, I'd wager that far less than 1% of instructions are going to do that:
Whatever the actual code is, the semiphore test condition and such are only a few machine instructions. The code that does the work might be thousands or tends of thousands of machine instructions. Basically, I think you'll end up with fine-grained threading benefiting a bit from the faster intercore bandwidth/latency, but it's not going to be an amazing improvement. A synthetic application to test just this "bottleneck" might be able to show a 25% improvement in intercore communication speed, but best case scenario I doubt it will end up being more than 2 to 5% faster in real code.
Yes, the more coarse grained your application is, the better it will do. The more coarse grained your application is, the less synchronization and data sharing between the threads. Fine grained is more synchronization and sharing. The synchronization costs (mutexs and such) can be small compared to the amount of MOESI traffic required when two simultaneously running threads actually work on the same data, that's why you typically try to partition the data across threads so that they share as little as possible (when you can do this, it isn't always possible depending on the algorithms you are using). I've seen benchmarks that supposedly share a bit of data between threads and that's where the dual-cores (AMD) do well compared to the dual socket/single core Opterons because the dual-core MOESI traffic overhead is a bit less than going off-chip. I haven't really seen much from the Intel side of things, though, but I would expect that they wouldn't be too much different from dual-socket/single-core Xeons if their MOESI traffic has to go off chip.
quote: The difference between communications sent over the FSB, through the chipset, and to a separate socket is going to be quite a bit larger than simply splitting the cores
I'm not so sure...the intercore communication on the split cores goes from the cache of CPU0, through the FSB to the Northbridge, and then back to the cache of CPU1. That's what happens on Smithfield as well...
The AMD example won't be quite as severe (2P vs DC) because the the intercore comms go directly via the HT link on 2P...
How much traffic is sent is a very good question, and frankly I have no idea (anyone else have an answer to this?).
No, AMD DC's comunicate through CrossBar switch, not via HT link.
Actually Smithfield was only a temporary measure, it is apparent Intel was able to design single die-multiple cores offering faster than multiple die-single package. Since the main reason for Smithfield is to have DC chips out ASAP, Intel has chosen the fastest route even if it meant it was more expensive. However with Presler Intel had enough time to perfect their Package&Chipset solutions to be able to accomodate 2 chips per package so the have chosen the more economical route this time.
I also believe the only single reason for 945/955 chipsets to exist was a premature release of PD. Now when Intel finally managed to make a chipset for Presler-like dualchip implementation, 945/955 are for no use except low-end offerings.
Anyway, IMHO Presler is much more dualchip solution the dualcore. Presler's SMP ability has almost nothing to do with the core itself. It is mostly the packaging& chipset issue exactly as with Xeon SMP implementation.
As of dualcore products are mostly from K8 family, Power5 family, Power 970 family, Yonah, most future Intel designs and to some extent Smithfield.
But Presler simply does not belong here.
Poetically said, Presler is product of the past while DC/MC is the future.
seems like there is lots of news from the intel front these days. People keep expecting intel to answer to amd's processor perfornmance effiency and power. But I don't here about any thing on the amd front. I am sure the gusy and amd are not sitting around waiting for intel to catch up, they must have something new in store besides a 1 more pin on a new socket.
I have to agree with Lal Shimpi that Intel's imminent CPUs are less than exciting. Progress is always good, but aside from the novelty of overclocking to over 4GHz there isn't much of a draw with CedarMill and Presler. However until AMD manages to make public some plans for innovation beyond new sockets, I think Intel has a good chance at overtaking AMD in the performance realm with slow and steady progress.
The competition between the two just isn't that hot right now. Hopefully things will get interesting when both copmanies release dual core mobile chips next year.
quote: However until AMD manages to make public some plans for innovation beyond new sockets, I think Intel has a good chance at overtaking AMD in the performance realm with slow and steady progress
Fair enough...but certainly not with a Netburst chip. If I were AMD, I probably wouldn't release much info at this point either...
1. As this shows, there really isn't any competition until the end of 06.
2. Anouncing any concrete changes early risk creating an http://en.wikipedia.org/wiki/Osborne_effect">Osbourne effect.
3. Anticipation of the new Intel architecture is too far down the track to cut into current AMD sales.
While there certainly are a few hints at some of the things to come (which AT mentions http://www.anandtech.com/cpuchipsets/showdoc.aspx?...">here), there have been any number of stealth releases from AMD in the past (for example, nobody knew how much cooler the Rev E chips would end up being).
Sadly for us, we just can't predict what is going to happen at the end of next year...
How good will Conroe (et al) actually perform?
What will AMDs products actually be?
Yea, the chips still consume a whole lot of power, but 4.25GHz dual core is very competitive - and from some leaked roadmaps, AMD has the X2-5000 on tap for Q1'06 as well.
I'm curious to know what the load temps were for those 4+GHz overclocks. And on the stock Intel HSF, right? I wonder what those crazy guys who use LN2 will get them too...
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43 Comments
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Beenthere - Friday, October 28, 2005 - link
In my not so humble opinion, one could write a doctorate thesis on the mistakes Intel has made in design and execution of it's PC products over the past 6 years. With today's announcement that Intel is canceling "White powder up Hotellini's nose" and "Tuck it up your butt Willy", you know the fools on the hill have no clue. As anyone in the IT industry knows, Intel does not respond well to competition let alone superior products by the competition. Intel has made one blunder after the other since AMD launched Athlon years ago. Intel has had repeated defective products, canceled products, delayed products, missed delivery dates, factory closings, chipset shortages requiring them to buy ATI chipsets, etc. The list of BLUNDERS by Intel is almost endless and continues as I write.http://www.theregister.com/2005/10/29/intel_xeon_2...">http://www.theregister.com/2005/10/29/intel_xeon_2...
Having a marginal 65 nano process at best, which actually just about competes on power consumption with AMD's 90 nano process, shows quite clearly that Intel is WAY behind the eightball despite the media hype! As history has shown, despite the years of denial, the P4 was a defective design rushed to market to try and kill Athlon, which it never accomplished. Now with Intel's most recent chip "delays" which will turn to cancellations next year, you will see some more cobbled crap from Intel that only losers would even consider buying.
So once again just as with their 90 nano process, that was according to Intel: "ahead of their development schedule", and then showed up in the marketplace over a year LATE and it was STILL a defective design as released with massive voltage leakage that required special cooling, cases, etc. Intel's 65 nano process hasn't even allowed them to catch up to AMD's existing products. It's all just hype and no substance, as usual for Intel.
What we have is Intel's PR machine spinning overtime as usual and no competitive products ANYWHERE in Intel's product line. They even lost their minimal advantage with the Pentium M in the laptop segment as the 25W and 35W Turions have stolen Intel's lunch. Bottom line is only a fool would buy any Intel product in the foreseeable future when AMD's products, by virtually all industry standards and reports, are far, far superior. It's encouraging to see consumers voting with their wallets. At least some consumers and industry sources have seen thru Intel's deception and purchased AMD products. Intel's days of extortion are pretty much over now that the cat is outta the bag.
IntelUser2000 - Friday, November 4, 2005 - link
Beenthere, how is having bad processor equate to having bad process technology??? Are most people that uninformed and stupid??? If Intel introduced Dothan for their first 90nm part, then people would have been praising Intel's 90nm process. Intel rather put Prescott out first, so people thought badly about it. If you DO read about what happened, focus has been all shifted to Merom/Conroe, OUT OF CEDARMILL/PRESLER PROJECTS. What happens then?? All the speedpath optimizations and low power optimizations that are supposed to go to Cedarmill/Presler went to Merom/Conroe. Merom will be ~30W DESPITE the fact its dual core, 4-wide architecture. Does Pentium M have low power compared to Prescott because its on a better process technology??? No.Intel has one of the best 90nm process, if not THE best.
Thatguy97 - Monday, May 25, 2015 - link
conroe proved you an idioteljefeII - Wednesday, October 26, 2005 - link
hehehe, yeah! yeah! intel s-s-smokes! yeah yeah!65 nm did like, um, a lot, yea, hhehhe. I don't see anything heheh, hehehhe. hehehhe.
Shut up beavis. Just like buy it and stuff.
hehhe yeah! buy it BUY IT BUY IT!!!
Zebo - Tuesday, October 25, 2005 - link
It's nice to see this will be a decent enthusiast chip.. Guys should get 1500-2000Mhz overclocks which will put some excitment into to the overclocking scene again. Sure stock they will suck but people I know don't run that way. A 4.5Ghz Cedar is fast no doubt about it probably equates to a 3Ghz A64 in a round table of benchmarks. As it happens 3Ghz seems pretty normal these days especially with the new Opteron 939's. So it would be great to hold a "overclockers shootout" of some sort when you guys have time. Say a 144 Opteron vs. Pentium 631 :DOne small error PP: 2 "Presler is physically two separate dice on a shared package,"
Die
danidentity - Wednesday, October 26, 2005 - link
The correct term is actually 'dies'. Dice is the plural form of die only when referring to the cube you play board games with. ;)yacoub - Wednesday, October 26, 2005 - link
This man is correct.coldpower27 - Tuesday, October 25, 2005 - link
Isn't Dice the plural form of Die though?GonzoDaGr8 - Tuesday, October 25, 2005 - link
DiesZebo - Tuesday, October 25, 2005 - link
Edit I meant presler and 930 respectivly.semo - Tuesday, October 25, 2005 - link
it is awfully tricky typing with left hand while spinning underpants with right hand and jumping up and down at the same timeyacoub - Tuesday, October 25, 2005 - link
I'm waiting until I can pick up a 5.0GHz dual core Intel chip with an 8MB L2 cache and frickin' flames painted on the sides of it.Griswold - Wednesday, October 26, 2005 - link
With sidepipes too! Pardon me, heat-sidepipes!mlittl3 - Tuesday, October 25, 2005 - link
For all of you asking about AMD's future, here is a link to an article with leaked AMD processor pricing guide (could be fake).http://www.avault.com/news/displaynews.asp?story=1...">http://www.avault.com/news/displaynews.asp?story=1...
Bascially, one can tell from the memo that the FX-60 will probably be dual core 2.8 GHz CPU (increments of 5 instead of two now to match Opteron plus two cores means +5 instead of +2) and there will be a dual core 2.6 GHz called 5000+. All of the single core Athlon 64s will be reduced in price to be below all the dual cores (except the 4000+ will be a little above the x2 3800+). All the semprons will be below single core athlons except the 3400+ sempron will be a bit above the 3000+.
Have fun dreaming of what you are going to buy. From the looks of things, AMD will be phasing out single core high speed processors sooner than we think. That means no 3.0 GHz in '06 Q1. :(
stephenbrooks - Tuesday, October 25, 2005 - link
Uhhh... I think the FX-60 is actually a 3.0GHz DDR2-667 single core part. Looks like the FX-59 3.0GHz DDR-400 got shelved, presumably to avoid confusion having two at the same clock speed but different memory.X2 5000+ ought to be 2.667GHz dual core on DDR2-667.
That is, if you believe this: http://www.c627627.com/AMD/Athlon64/">http://www.c627627.com/AMD/Athlon64/
JarredWalton - Wednesday, October 26, 2005 - link
Not your fault, but I don't believe they have the details correct on that site. In fact, I'm almost sure of it.333 MHz CPU bus speed seems questionable at best to me. We might get that, but right now even the best 939 motherboards get flaky above 300 MHz CPU bus, and DDR2 isn't going to fix that. I'm inclined to think that AMD would go with a 266 bus instead, but really I don't think they'll even do that.
Why? Simple: RAM speed on AMD systems is really independent of CPU bus speed. So, you can have a 200 MHz CPU bus with 1000 MHz HyperTransport, and the RAM can run at anything you want! (The RAM speed is derived from the CPU speed and has nothing to do with the CPU bus speed.) The 1000 MHz HT bus listed leads me to believe AMD will stick with a 200 MHz base CPU bus speed and 5X HT multiplier. The only change will be that instead of a CPU/12 divider on the 2.4 GHz chip, they'd have a CPU/8 divider. (That would actually result in DDR2-600, but since CPU/7 would give DDR2-686, they'll have to stick to the lower speed.)
Given that information, my guess is that the X2 5000+ will actually be the same as the X2 4800+, only with DDR2-667 support on socket M2. In other words, my bet right now is that M2 5000+ will be 2.4 GHz. It makes sense: the socket shift will almost certainly come with a speed increase, and so AMD will have different model numbers for the new sockets. It will basically be like the past: 2.2 GHz 754 is a 3200+ while the 2.2 GHz 939 is a 3500+.
stephenbrooks - Wednesday, October 26, 2005 - link
Yeah the guy changed his roadmap just this afternoon! Sorry about that.A shame really, I'd have liked to see the higher bus, but as you say it's a big jump from the current technology.
mlittl3 - Wednesday, October 26, 2005 - link
I agree with Jared about the FSB. The FSB is not the same on the Athlon 64's as the Athlon XP's and the Pentium 4's, Stephenbrooks. You can't just go to 333 MHz to match the ddr2 memory speeds. The FSB if you can even call it that will always be a HT bus running in half or full duplex mode and will probably stay a multiple of 200 for awhile. Just my guess.But I disagree with Jared about what the chips are in the leaked pricing memo. If it is a true memo, then I think all processors on it are Socket 939 (no DDR2). It says Q1 '06 and I think the new sockets from AMD are not due until March. We are seeing the last of the Socket 939 processors and I think they are trying to move to all dual core similar to intel. Dual core on the FX processor (2.8 GHz giving 5 increment model numbers like the opterons) and a 200 MHz bump on the X2 5000+ to 2.6 GHz. We were all expecting a 2.6 GHz dual core part but a 2.8 GHz is a little iffy without the 65 nm shrink to keep things consuming less power.
Oh well, only time will tell.
JarredWalton - Wednesday, October 26, 2005 - link
Oh, I didn't look at the AV link, mlitt, so I wasn't referring to that information. I'm still wondering what the 5000+ will be. If you look at the clock speeds and past performance, Toledo at 2.6 GHz is almost certainly a 5200+, while Manchester at 2.6 GHz would be the 5000+.2.6 / 2.4 = 1.08333 (8.33% speed increase)
4800 * 1.08333 = 5200
4600 * 1.08333 = 4983
I'd guess we'll see a couple 2.6 GHz socket 939 X2 chips in early 2006. I could be wrong on the socket shift and AMD will just use the same names for the same speed, but the 754 to 939 shift indicates that they like to take advantage of faster platform performance by increasing the model number, so I really don't think they'll do that. If M2 chips are 5% faster than 939 chips, there's no way the marketing department will let that pass by without some hype. :) Besides...
4800 * 1.05 = 5040
4600 * 1.05 = 4830
If the 5% guess is correct, I expect a 200 point model number change. Though it would be nice if they actually didn't overlap numbers, so in the above two instances they could call the 2.4 GHz 512K/1MB M2 chips the 5050+ and 4850+. Wouldn't it be great to actually have less obfuscated performance for once?
mongoosesRawesome - Tuesday, October 25, 2005 - link
I really appreciate this article. Curious as to how you secured these chips without having to sign an NDA.AMD's A64s need to be able to reach 3.0 GHz in order for them to stay competitive with these new 65nm intel chips on the overclocking front. While some of their venice chips are definitely reaching those speeds, especially with a decent voltage bump, most don't quite make it. I expect that by the time these 65nm chips come out though, a 3.0 GHz OC on a 3800+ dual core system should be the norm. Competition is good, now we just need intel to lower their price on their motherboards and not attempt to restrict OCing on their motherboards chipsets.
Griswold - Tuesday, October 25, 2005 - link
I didnt see anything about (real) stability and throttling.POV-Ray is all nice and such, but does it put as much stress on the core(s) as, let's say, S&M 1.7.3?
Also, I havent seen any temperatures. :)
Granted, it's just a preview, but still. I'm mostly interested in throttling. 4.5GHz on CPU-Z is cool, but does it deliver that when you heat up the kitchen?
tuteja1986 - Tuesday, October 25, 2005 - link
Is Intel back in the high performance section ? Can they finally defeat AMD in gaming benchmark ? What does AMD in store for us ? Do you guys think that Intel are going to pawn AMD ? : ( Question ... Anyways this is a good sign of competition from Intel and i am know interested in getting a Intel 65nm if they perform good and be very competitive in gaming benchmark.Shintai - Tuesday, October 25, 2005 - link
65nm P4s are only a temporary thing. They sued the 65nm to gain benefits inmaking a cheaper product, while getting better in the performance/watt issue and getting the P4 into acceptable powerlevels and heatlevels.However..Intel gives a damn about 4Ghz P4 etc for one reason. Conroe will burrow P4 in week 36 2006. And Yonah will take a huge part aswell until Conroe/Merom. Netburst is dead, all hail Pentium-M and it´s successor.
KristopherKubicki - Tuesday, October 25, 2005 - link
The first gen 65nm are definitely a temporary thing. As we all have seen from the roadmaps, Conroe is the real chip.Kristopher
NullSubroutine - Tuesday, October 25, 2005 - link
I found it very interesting that Intel actually put two seperate cores and dies on the new dual core chip. This is very interesting as it affects pricing but decreasing cost (of defective dies) thus places this processor in a possibly lower pricing point than AMD's. And if you like heavy encoding where netburst has always done well in, this chip could be your best bet, espeically if the increase in cache increases the benchmarks like the P4 notably has with such. IMHOViditor - Tuesday, October 25, 2005 - link
It does indeed increase yield (thus decreasing cost), however we have no way of knowing how good the original yield is, so they may still be more expensive to produce.
It also decreases performance by increasing the latency between cores and increasing the bandwidth requirements of the FSB...
JarredWalton - Tuesday, October 25, 2005 - link
I have to say that I'm a little skeptical on the whole core-to-core bandwidth topic. I think there's a lot less inter-core communication than some people think. The FSB latency and bandwidth is the bigger question, so really I doubt that having split cores (Presler) is any worse than Smithfield - the extra cache probably more than compensates.Of course, X2 still has the latency advantage (by a huge margin), but I'm only looking at the Intel side here. I mean, we can't really draw any conclusions from Presler vs. Toledo other than to (most likely) say that Toledo is faster. Why it's faster is almost certainly due more to the overall architecture and design than the faster inter-core communication.
It will be interesting to see if Intel can get latencies down with future chips without resorting to an integrated memory controller. I believe at present Intel's best is around 100ns latency for RAM while AMD is 30 to 40ns. If Intel could even get their chips to 75ns, it would be a huge improvement.
Viditor - Tuesday, October 25, 2005 - link
Fair enough Jarred...but we can probably get a good idea of the core to core advantages by comparing a dual core Opteron to a 2P Opteron rig at the same speeds...As to Presler v Smithfield, maybe I'm confused but isn't Smithfield a split core as well? Any corrections greatly appreciated!
JarredWalton - Tuesday, October 25, 2005 - link
Heh - from this article by Anand, I gathered that Smithfield wasn't split and Presler is. Needless to say, I haven't personally pried off the heat spreader on my Smithy, so I don't know for sure. :) (I'm also open to enlightenment if someone has definite evidence - I'm being too lazy to research it right now!)2P Opteron vs. DC Opteron isn't quite the same as split core vs. single core, though. The difference between communications sent over the FSB, through the chipset, and to a separate socket is going to be quite a bit larger than simply splitting the cores. I'm sure a unified core has faster inter-core communication speeds, but the question is: how fast do they need to be?
If such signaling only occurs on rare occasions, the real world performance difference between split cores and unified cores (of dual-core packages) may be less than 1 or 2 percent in real-world testing. There's also the question of 2P vs. DC on Intel in contrast to the same on AMD. Intel tends to have more bus bandwidth and lower latency, and perhaps better RAM prefetch logic as well. Opteron DC might be 5 to 10% faster while Intel would only be 2% faster, or maybe it's the reverse of that. (Again, I'm being lazy.)
Basically, since the architectures of NetBurst and K8 are vastly different, DC/SMP/etc. can benefit - or not - from technologies to varying degrees. And yes, I realize for many that's going to be a "duh!" statement. "Hey people - bananas are very different from oranges!" Shock and awe.... Still, it bears mention since we still have people out there that don't understand that pipeline stages, architectural designs, etc. are at least as important as raw clock speeds.
AndreasM - Tuesday, October 25, 2005 - link
http://images.google.com/images?q=smithfield+intel">Google smithfield+intelhighlandsun - Tuesday, October 25, 2005 - link
Core-to-core is extremely important in a lot of multi-threaded applications. Remember that the programming model for threading is that multiple threads share one address space and so have shared access to data. Thread synchronization with mutexes and such requires that all processors have fast access to the mutex variables. As such, core-to-core communication is crucial.Viditor - Tuesday, October 25, 2005 - link
Thanks highland...some other questions if you could help.Do you have any idea as to how much bandwidth would increase for just the core to core traffic during multitasking?
What effect would increased latency for the core to core have on overall multitasking?
JarredWalton - Tuesday, October 25, 2005 - link
I should also mention that DC could actually be slower than 2P in cases where you have say 2 DIMMs per socket and a UMA-aware OS.Here's the real problem, Highland: in theory faster core-to-core speeds are important for SMP code. In reality, mutex and thread synchronization is bad. You don't want SMP software to spend a lot of time waiting to enter exclusive code blocks. In an ideal SMP application, you spend a fraction of time splitting up a task into two equal halves, then you let two cores churn away on those tasks for a relatively long time, and then you spend a fraction of time combining the results/synchronizing. If you're spending a lot of effort on thread synchronization, then you've got a task or algorithm that doesn't work very well for SMP in the first place.
This is more guesswork and supposition than actual knowledge. If someone has a concrete set of benchmarks that show real-world SMP doing much better (or worse!) on DC vs. 2P, I'd love to hear about it. If you can prove that the faster core-to-core speeds are what leads to better results in a real scenario, I'd like to hear about the application as well. Maybe I'm just not being creative enough, but I'm having a difficult time coming up with a task that's going to do great on SMP and also show a marked improvement on DC vs. 2P. The more independent the pieces of a task are, the better it will do on SMP setups, and conversely the less important core-to-core signaling becomes.
highlandsun - Tuesday, October 25, 2005 - link
Yes, "an ideal SMP application" may allow coarse grained division of labor. That may apply to supercomputing applications, where array/vector operations tend to dominate. That's a good model of SIMD computing, but that isn't the only model that users will run into.I think that class of problem is actually pretty rare. More often you need concurrent access to shared data. E.g., a web server with lots of front-end tasks talking to a multi-threaded database server. Since any number of threads may be writing new data while other threads are querying for data, all data accesses must be synchronized. For this class of problem, I expect the AMD design will have a noticable advantage.
This is significant, because I believe this class of problem is far more relevant in every day use. Think of the filesystem drivers in your OS, the databases behind big search engines like Google, etc., they're all about moderating multiple accessors to shared data. The faster your core-to-core communication, the better you can handle this type of task, and you run into this task every minute that you touch a computer.
JarredWalton - Wednesday, October 26, 2005 - link
There will be a few areas it helps, but I really don't think it will matter much. Most mutex accesses will be a very small fraction of the total compute time. Let's say that in a given second, you have 2 billion operations that a CPU can execute. How many of those will have to do with core-to-core work? If I were to take a stab at a figure, I'd wager that far less than 1% of instructions are going to do that:if(checkmutex()) {
do_massive_subroutine();
}
else {
wait();
}
Whatever the actual code is, the semiphore test condition and such are only a few machine instructions. The code that does the work might be thousands or tends of thousands of machine instructions. Basically, I think you'll end up with fine-grained threading benefiting a bit from the faster intercore bandwidth/latency, but it's not going to be an amazing improvement. A synthetic application to test just this "bottleneck" might be able to show a 25% improvement in intercore communication speed, but best case scenario I doubt it will end up being more than 2 to 5% faster in real code.
fitten - Tuesday, October 25, 2005 - link
Yes, the more coarse grained your application is, the better it will do. The more coarse grained your application is, the less synchronization and data sharing between the threads. Fine grained is more synchronization and sharing. The synchronization costs (mutexs and such) can be small compared to the amount of MOESI traffic required when two simultaneously running threads actually work on the same data, that's why you typically try to partition the data across threads so that they share as little as possible (when you can do this, it isn't always possible depending on the algorithms you are using). I've seen benchmarks that supposedly share a bit of data between threads and that's where the dual-cores (AMD) do well compared to the dual socket/single core Opterons because the dual-core MOESI traffic overhead is a bit less than going off-chip. I haven't really seen much from the Intel side of things, though, but I would expect that they wouldn't be too much different from dual-socket/single-core Xeons if their MOESI traffic has to go off chip.Viditor - Tuesday, October 25, 2005 - link
I'm not so sure...the intercore communication on the split cores goes from the cache of CPU0, through the FSB to the Northbridge, and then back to the cache of CPU1. That's what happens on Smithfield as well...
The AMD example won't be quite as severe (2P vs DC) because the the intercore comms go directly via the HT link on 2P...
How much traffic is sent is a very good question, and frankly I have no idea (anyone else have an answer to this?).
mino - Tuesday, October 25, 2005 - link
No, AMD DC's comunicate through CrossBar switch, not via HT link.Actually Smithfield was only a temporary measure, it is apparent Intel was able to design single die-multiple cores offering faster than multiple die-single package. Since the main reason for Smithfield is to have DC chips out ASAP, Intel has chosen the fastest route even if it meant it was more expensive. However with Presler Intel had enough time to perfect their Package&Chipset solutions to be able to accomodate 2 chips per package so the have chosen the more economical route this time.
I also believe the only single reason for 945/955 chipsets to exist was a premature release of PD. Now when Intel finally managed to make a chipset for Presler-like dualchip implementation, 945/955 are for no use except low-end offerings.
Anyway, IMHO Presler is much more dualchip solution the dualcore. Presler's SMP ability has almost nothing to do with the core itself. It is mostly the packaging& chipset issue exactly as with Xeon SMP implementation.
As of dualcore products are mostly from K8 family, Power5 family, Power 970 family, Yonah, most future Intel designs and to some extent Smithfield.
But Presler simply does not belong here.
Poetically said, Presler is product of the past while DC/MC is the future.
mrgq912 - Tuesday, October 25, 2005 - link
seems like there is lots of news from the intel front these days. People keep expecting intel to answer to amd's processor perfornmance effiency and power. But I don't here about any thing on the amd front. I am sure the gusy and amd are not sitting around waiting for intel to catch up, they must have something new in store besides a 1 more pin on a new socket.GlobalAmityPeter - Tuesday, October 25, 2005 - link
I have to agree with Lal Shimpi that Intel's imminent CPUs are less than exciting. Progress is always good, but aside from the novelty of overclocking to over 4GHz there isn't much of a draw with CedarMill and Presler. However until AMD manages to make public some plans for innovation beyond new sockets, I think Intel has a good chance at overtaking AMD in the performance realm with slow and steady progress.The competition between the two just isn't that hot right now. Hopefully things will get interesting when both copmanies release dual core mobile chips next year.
http://globalamity.net">GlobalAmity.net
Viditor - Tuesday, October 25, 2005 - link
Fair enough...but certainly not with a Netburst chip. If I were AMD, I probably wouldn't release much info at this point either...
1. As this shows, there really isn't any competition until the end of 06.
2. Anouncing any concrete changes early risk creating an http://en.wikipedia.org/wiki/Osborne_effect">Osbourne effect.
3. Anticipation of the new Intel architecture is too far down the track to cut into current AMD sales.
While there certainly are a few hints at some of the things to come (which AT mentions http://www.anandtech.com/cpuchipsets/showdoc.aspx?...">here), there have been any number of stealth releases from AMD in the past (for example, nobody knew how much cooler the Rev E chips would end up being).
Sadly for us, we just can't predict what is going to happen at the end of next year...
How good will Conroe (et al) actually perform?
What will AMDs products actually be?
Doormat - Tuesday, October 25, 2005 - link
Yea, the chips still consume a whole lot of power, but 4.25GHz dual core is very competitive - and from some leaked roadmaps, AMD has the X2-5000 on tap for Q1'06 as well.I'm curious to know what the load temps were for those 4+GHz overclocks. And on the stock Intel HSF, right? I wonder what those crazy guys who use LN2 will get them too...
Kalessian - Tuesday, October 25, 2005 - link
Yawn, I overclocked my 1.8ghz Venice by 1gz a long time ago, and 1ghz on a K8 is much more powerful than 1ghz on a p4.You guys should have tested the lower end CPUs (2.8ghz or 3.2ghz) to test the limits. If those could push a 1500mhz+ increase I'd be impressed.
I bet I run cooler, too.
Not that progress is bad, mind you. I'm all for 65nm.