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  • Maverick Shiva - Thursday, November 25, 2004 - link

    The Articles are really beautiful.
    This was the complete description of the processors that are released and yet to be released.

    The technical details are really awsome and minute to the Detail.

    I would recommend that if you had Anand Tech.com then you are really tech Savvy.
  • JarredWalton - Saturday, September 18, 2004 - link

    #72 - the article is now slightly outdated, being a whopping 20 days old. Sorry. We'll look at updating this with future articles, of course.
  • Assimilator1 - Friday, September 17, 2004 - link

    An excellent article:)

    Though as someone mentioned the Semperon 2300 is missing ,this is clocked at 1.583GHz.
    Its listed in AMDs model 8 data sheets
  • endrebjorsvik - Wednesday, September 15, 2004 - link

    A very nice article with lost of good information!!

    Is there anybody who has all these datas collected into somethong like an exel-file or something.
  • jenand - Wednesday, September 8, 2004 - link

    JarredWalton: If you are going to update the roadmaps. Here is some good Itanium Info:
    http://www.intel.com/design/itanium2/download/Madi...
  • jenand - Wednesday, September 8, 2004 - link

    JarredWalton: If you are going to update the roadmaps. Here is some good Itanium Info:
    http://www.intel.com/design/itanium2/download/Madi...
  • romanl - Tuesday, September 7, 2004 - link

    Why is the Sempron 2300+ missing from a list of AMD CPUs?
  • IntelUser2000 - Thursday, September 2, 2004 - link

    It was said that Willamette has 33% superior branch prediction due to its 4KB BTB buffer compared to Pentium III's(P3's had 512B).

    It was also said Pentium M's have 20% superior branch prediction to previous generation. Since we know that the major enhancements on branch prediction for Pentium M is enhanced indirect branch prediction and no BTB buffer increase, its likely its 20% over P3.

    Dothan does have superior branch prediction to 0.13 micron Pentium M, but it would probably be minor compared to Pentium 4's 33% superiority over P3.

    Taking P3 as baseline,
    -Pentium 4 adds 33% using 8x increase in BTB buffer, or 4KB compared to 512B
    -Banias takes P3 and puts enhancements to indirect branch predictor, which gives 20%
    -Prescott takes 33% from Willamette AND 20% from Banias
    -Dothan has Banias' 20% improvements plus something minor

    You say: " However, with the doubling of the cache size on Dothan, I can't imagine Intel would leave it with inferior branch prediction."

    Yeah but I can't imagine that Prescott will have inferior branch prediction than Dothan since its needed more on Prescott. And looking at per clock enhancements Dothan is not much faster than Banias, except Content Creation apps, telling again the enhancements are minor.


    Remember we are talking about how superior one branch predictor would be over another with same pipelines.

    I think of it this way: In terms of worst to best

    Pentium III
    Banias
    P4 Willamette/Northwood/Dothan(I still think 33% improvement over P6 is greater than 20% in Banias+Dothan improvements)
    Prescott


    Oh yeah, there will be 4MB Fanwood parts but at 1.6GHz.

    Also since Itanium's core is half the size of Xeon and Intel also mentioned there will be twice the number of cores that Xeon has and Tukwila will be introduced ~2007 with quad-core Xeon then, Tukwila will have 8-core with Hyperthreading. Montecito is rumored to already have 600mm2 die size. Montecito has 24MB but Tukwila is rumored to have 32MB, not a lot increase, to possibly save space for more cores?

    I mean, Sun plans 32-core designs.

    Link: www.mikeshardware.co.uk
  • JarredWalton - Wednesday, September 1, 2004 - link

    Jenand, just an update, but it appears that Fanwood might not have 9M parts. The latest Intel roadmap talks about "Madison 9M/Fanwood/LV" parts in several places, but all the actual Fanwood parts are listed as 3M parts, and there's a not about pushing back the Fanwood 4M part.

    What is Fanwood? As of right now, I'm really not sure. Initially, I thought it was a renamed Madison, perhaps with more cache or for LV environments. Now, I'm starting to wonder if it might be a 90 nm version of Madison, or a version with more metal layers. Clock speeds are still in the Madison range, so that wouldn't really make sense, but why have the separate name if it's not somehow fundamentally different from Madison?

    And for what it's worth, the charts are now outdated somewhat with the announcement of the 6xx series of 2M L2 Pentium 4 parts. See latest Insider Stories.
  • jenand - Wednesday, September 1, 2004 - link

    Yes, Fanwood looks to be a 9MB L3 part. Strange. But i is limited to DP servers while Madison9M is for MP servers. just like Xeon MP end DP I guess.

    And no not many care about IA64 these days. Not strange. But with Millington I assume that will change! ;)
  • JarredWalton - Wednesday, September 1, 2004 - link

    Jenand - thanks for the information. There are certainly some errors in the Itanium charts, but very few people seem to know much about the architecture, so I haven't gotten any corrections. Most of the future IA64 chips are highly speculative in terms of featurs.

    Incidentally, it looks like Tukwilla (and Dimona) will be 4 core designs, with motherboards support 4 CPUs, thus "16C" - or something like that. As for Fanwood, I really don't know much about it other than the name and some speculation that it *might* be the same as Madison9M. Or it might be a Dual Processor version of Madison, which is multi-processor.

    http://endian.net/details.asp?ItemNo=3835
    http://www.xbitlabs.com/news/cpu/display/200311101...

    At the very least, Fanwood will have more than just a 9 MB cache configuration, it's probably safe to say.
  • JarredWalton - Wednesday, September 1, 2004 - link

    If Prescott and Pentium M both use the exact same branch predictor, then yes, the Prescott would be more accurate than Banias. However, with the doubling of the cache size on Dothan, I can't imagine Intel would leave it with inferior branch prediction. So perhaps it goes something like this in terms of branch prediction accuracy:

    P6 cores
    Willamette/Northwood
    Banias
    Prescott
    Dothan

    Possibly with the last two on the same level.

    I'm still waiting to see if we can get pipeline stage information from Intel, but I have encountered several other sources online that refer to the Willamette/Northwood as having a 28 stage pipeline. Guess there's no use in beating a dead horse, though - either Intel will pass on information and we can have a definite, or it will remain an unknown. Don't hold your breath on Intel, though. :)
  • IntelUser2000 - Wednesday, September 1, 2004 - link

    "Intel claims that the combination of the loop detector and indirect branch predictor gives Centrino a 20% increase in overall branch prediction accuracy, resulting in a 7% real performance increase."

    Sure, but Prescott also has Pentium M's branch predictor enhancements in addition to the enhancements made to Willamette, while Pentium M didn't get Willamette's enhancements, just the indirect branch predictor.

    Yes it says 20% increase, but from what? PIII, P4? Prescott?
  • jenand - Tuesday, August 31, 2004 - link

    There are a few errors and some missing information on the IPF sheet:
    1) Fanwood will get 4M(?) L3 or so, not 9M. You probably mixed it up with its bigger brother Madison9M, both to be released soon.

    2)Foxton and Pelleston are code names for technologies used in Montecito, not CPU code names.

    3) Dimona and Tukwila are "pairs" (just like Madison/Deerfield, Madison9M/Fanwood and Montecito/Millington) both will be made on 45nm nodes and are scheduled for 2007. Montvale is probably a shrink of Montecito or Millington to the 65nm node and will probably be launched in 2006.

    4) Montecito and Millington will be made on 90nm and use the PAC-611 socket. The FSB of Montecito will be 100MHZ for compatibility reasons, but will also be introduced at a higher FSB (166MHz?) late in 2005.

    5) Fanwood will probably get 100MHz and 133MHz FSB, not 166MHz. Same goes for Millington.

    I hope it was helpful. Please note that I don't have any internal information I only read the rumors.
  • JarredWalton - Tuesday, August 31, 2004 - link

    Heh... one last link. Hannibal discusses why the PM is able to have better branch prediction with a smaller BTB in his article about the PM. At the bottom of the following page is where he specifically discusses the improvements to the P4:

    http://castor.arstechnica.com/cpu/004/pentium-m/pe...

    And his summary: "Intel claims that the combination of the loop detector and indirect branch predictor gives Centrino a 20% increase in overall branch prediction accuracy, resulting in a 7% real performance increase. Of course, the usual caveats apply to these statistics, i.e. the increase in branch prediction accuracy and that increase's effect on real-world performance depends heavily on the type of code being run. Improved branch prediction gives the PM a leg up not only in terms of performance but in terms of power efficiency as well. Because of its improved branch prediction capabilities, the PM wastes less energy speculatively executing code that it will then have to throw away once it learns that it mispredicted a branch."

    He could be wrong, of course, but personally I trust his research on CPUs more than a lot of other sites - after all, he does *all* architectures, not just x86. Hopefully, Intel will provide me (Kristopher) with some direct answers. :)
  • JarredWalton - Tuesday, August 31, 2004 - link

    In case that last wasn't clear, I'm not saying the CPU detection is really that blatant, but if the CPU detection is required for accuracy, it *could* be that bad. Rumor, by the way, puts the Banias core at 14 or 15 stages, and the Dothan *might* add one more stage.
  • JarredWalton - Tuesday, August 31, 2004 - link

    Regarding Pentium M, I believe the difference to the branch prediction isn't merely a matter of size. It has a new indirect branch predictor, as well as some other features. Basically, P-M is designed for power usage first, and so they made a lot more elegant design decisions at times, whereas Northwood and Prescott are more of a brute force approach.

    As for the differences between various AT articles, it's probably worth pointing out that this is the first article I've ever written for Anandtech, so don't be too surprised that it has some differences of opinion. Who's right? It's difficult to say.

    As for the program mentioned in that thread, I downloaded it and ran it on my Athlon 64. You know what the result was? 13.75 to 13.97 cycles. Since a branch miss doesn't actually necessitate a flush of the entire pipeline, that would mean that it's estimating the length of the A64 as probably 15 or 16 stages - off by a factor of 33% or so. If it were off by that same amount on Prescott, that would put Prescott at [drumroll...] 23 stages.

    I've passed on some questions for Intel to Kristopher Kubuki, so maybe we can get the real poop. Until then, it's still a case of "nobody knows for sure". Estimating pipeline lengths based off of a program that reports accurate results on P4 and Northwood cores is at best a guess, I would say.

    Incidentally, I looked at the source code, and while I haven't really studied it extensively, there is a CPU detection, so the mispredict penalty is calculated differently on P4, P6, and *other* architectures. Maybe it's okay, maybe it's not, but if accurate results are dependent on CPU detection, that sort of calls the whole thing into question.

    if CPU=P6 then printf("12 stages.\n")
    else if CPU=P4 then printf("10 stages.\n")
    else if....

    Hopefully, it *is* relatively accurate, but as I said, ~14 cycles mispredict penalty on an Athlon 64 is either incorrect, or AMD actually created a 15 stage pipeline and didn't tell anyone. :)
  • IntelUser2000 - Monday, August 30, 2004 - link

    Okay, I don't know further than that. But one question: Since the old P4 article from Anandtech states 10 stage pipelin P6 core, and Prescott is claimed to have 31 stages and you claim otherwise, it tells that there is individual errors in the SAME site. So whether Hannibal's site can be trusted is doubtful because of that fact too, no? Also, take a look at this link: http://www.realworldtech.com/forums/index.cfm?acti...

    I asked a guy in the forums about it and that link is about the responses to it.

    One example Hannibal's site may be wrong is this: http://arstechnica.com/cpu/004/prescott-future/pre...

    At the end of that link it says: "There's actually another reason why the Pentium M won't benefit as much from hyperthreading. The Pentium M's branch predictor is superior to Prescott's, so the Pentium M is less likely to suffer from instruction-related pipeline stalls than the Prescott. This improved branch prediction, in combination with its shorter pipeline, means improved execution efficiency and less of a need for something like hyperthreading."

    Now, we know Pentium M has shorter pipeline than Prescott but better branch prediction? I really think its wrong, since one of the major improvements of BOTH Prescott and Pentium M in branch prediction is improvements in indirect branch prediction, PLUS, Prescott and Northwood I believe, has bigger BTB buffer size, somewhere in the order of 8x, because Pentium M used indirect branch prediction improvements to save die size and putting more buffer definitely doesn't coincide with that.
  • Fishie - Monday, August 30, 2004 - link

    This is a great summary of the processor cores. I would like to see the same thing done with video cards.
  • JarredWalton - Monday, August 30, 2004 - link

    #49 - Did you even read the links in post #44? Did you read post #44? Let's make it clear: the Willamette and Northwood cores were 20 stage pipelines coupled to an 8 stage prefetch/decode unit (which feeds into the trace cache). This much, we know for sure. The Prescott core appears to be 23 stages with the same (essentially) 8 stage prefetch/decode unit. So, you can call early P4 cores 20 stages, in which case Prescott is 23 stages, or you can call Prescott 31 stages, in which case early P4 cores were 28 stages.

    If you look at the chart in the link to Anandtech, notice how the P4 pipeline is lacking in fetch and decode stages? Anyway, there's nothing that says the AT chart you linked from Aug 2000 is the DEFINITIVE chart. People do make errors, and Intel hasn't been super forthcoming about their pipelines. I'll give you a direct link to where Hannibal talks about the P6 and P4 pipelines - take it up with him if you must:

    http://arstechnica.com/cpu/004/pentium-1/pentium-1...

    Synopsis: In the AT picture, the P6 pipeline has 2 fetch and 2 decode stages, while Hannibal describes it as 3.5 BTB/Fetch stages and 2.5 Decode stages.

    http://arstechnica.com/cpu/01q2/p4andg4e/p4andg4e-...

    Here, the P4 and G4e architectures are compared, but if you read this page, it explains the trace cache and how it effects things. Specifically: "Only when there's an L1 cache miss does that top part of the front end kick in in order to fetch and decode instructions from the L2 cache. The decoding and translating steps that are necessitated by a trace cache miss add another eight pipeline stages onto the beginning of the P4's pipeline, so you can see that the trace cache saves quite a few cycles over the course of a program's execution."
    -----------------------
    Further reading:

    http://episteme.arstechnica.com/eve/ubb.x?a=tpc&am...

    The comments in the "Discuss" section of the article contain further elaboration by Hannibal on the Prescott: "The 31 stages came from the fact that if you include the trace cache in the pipeline (which Intel normally doesn't and I didn't here) then the P4's pipeline isn't 20 stages but 28 (at least I think that's the number). So if you add three extra stages to 28 you get 31 total stages."

    The problem is, Intel simply isn't coming out and directly stating what the facts are. It *could* be that Prescott is really 31 stages (as Intel has said) plus another 8 to 10 stages of fetch/decode logic, putting the "total" length at 39 to 41 stages. However, given the clockspeed scaling - rather, the lack thereof - it would not be surprising to have it "only" be 23 stages plus 8 fetch/decode stages. After all, the die shrink to 90 nm should have been able to push the Northwood core to at least 4 GHz, which seems to be what the Prescott is hitting as well.

    Unless you actually work for Intel and can provide a definitive answer? I, personally, would love some charts from Intel documenting all of the stages of both the initial NetBurst pipeline as well as the Prescott pipeline. (Maybe I should mention this to Anand...?)
  • JarredWalton - Monday, August 30, 2004 - link

    #50 - Good catch. Obviously, there was some cutting and pasting involved. At some point, I corrected all of the names, but missed some of the clock speeds (at least on the Intel charts).

    #53 - Yes, you are correct. Someone corrected me before, but I didn't change both AMD charts. The Clawhammer supposedly does not have all three HyperTransport paths, so the FX would have to use the Sledgehammer core. It's just a little odd trying to figure out what AMD is doing on those cores. If it were Intel, every core version (i.e. different cache size, different memory controller, different socket) would probably get its own name. :)
  • OC DETECTIVE - Monday, August 30, 2004 - link

    Actually #25's assertion that the FX 939 is a Clawhammer is incorrect. See details of correspondence with AMD's technical dept.over here
    it is a Sledgehammer!
    http://www.xtremesystems.org/forums/showthread.php...
  • Pumpkinierre - Sunday, August 29, 2004 - link

    #49 There was a post not so long back that had the Prescott pipeline at 22 stages. But your information is right at launch. I just wonder how valid all this pipeline model is or whether the processor takes what it needs for the task required.
  • karlreading - Sunday, August 29, 2004 - link

    very informative article, very handy when talking hardware!!!
  • heintjeput2 - Sunday, August 29, 2004 - link

    A found a few things who are probably wrong
    P4 2.2 2800 Northwood 512 100 28.0X 478
    should be:
    P4 2.2 2200 Northwood 512 100 22.0X 478

    and:
    P4 3.2E 3800 Prescott 1024 200 19.0X 478
    should be:
    P4 3.2E 3200 Prescott 1024 200 16.0X 478

    P4 540/J 3800 Prescott 1024 200 19.0X T/775
    should be:
    P4 540/J 3200 Prescott 1024 200 16.0X T/775

    P4 3.2C 3800 Northwood 512 200 19.0X 478
    >>
    P4 3.2C 3200 Northwood 512 200 16.0X 478

    P4EE 3.2 3800 Gallatin 512 200 19.0X 478 2048
    >>
    P4EE 3.2 3200 Gallatin 512 200 16.0X 478 2048

    PM 1.2 (LV) 1800 Banias 1024 100 18.0X 478M
    >>
    PM 1.2 (LV) 1200 Banias 1024 100 12.0X 478M ??

    MP4 3.2 HT 3800 Northwood 512 133 28.5X 478M
    >>
    MP4 3.2 HT 3200 Northwood 512 133 25.5X 478M

    Athlon XP-M 2600+ 1933 Barton 512 133.3 14.5X
    >>
    Athlon XP-M 2600+ 2000 Barton 512 133.3 15.0X

    Sempron 3100+ 1800 Paris** 256 200 9.0X 754
    >>
    Sempron 3100+ 1800 Paris* 256 200 9.0X 754
    add:
    Athlon XP-M 2400+ (ULV) 1800 Barton 512 133.3 13.5X
    Athlon XP-M 2400+ (LV) 1800 Barton 512 133.3 13.5X
    Athlon XP-M 2500+ (LV) 1867 Barton 512 133.3 14.0X
    Athlon XP-M 2600+ (LV) 2000 Barton 512 133.3 15.0X
  • IntelUser2000 - Sunday, August 29, 2004 - link

    I don't understand why people don't look up at Anandtech's old articles for information(or at least don't seem to)

    Take a look at the Pentium 4 Willamette article that states 10-stage pipeline for Pentium III and 20-stage pipeline for Pentium 4. I believe the most common figures are the Integer pipelines not including fetch/decode stages(according to your article anyway).

    Link to article: http://www.anandtech.com/cpuchipsets/showdoc.aspx?...

    Also why does it say Prescott have 23 stage pipelines?

    "The Prescott further extended the NetBurst pipeline to 23 stages in addition to the 8 fetch/decode stages. For whatever reason, Intel generally describes the pipeline of the Prescott as 31 stages while only calling the earlier design a 20 stage pipeline."
  • JarredWalton - Sunday, August 29, 2004 - link

    47 - Somehow I screwed that up in the update. Sorry. The 133 MHz bus (533 FSB) Xeon chips run in socket 604, so the two later Prestonia core Xeons are socket 604 parts. As far as I know, all the Gallatin Xeon cores are still socket 603.
  • Marlin1975 - Saturday, August 28, 2004 - link

    ALL the P4 Xeons are listed at socket 603. I know the later and even current ones are now 604.
  • Zebo - Saturday, August 28, 2004 - link

    One of the best guides I even read thanks I learned a lot.:)
  • JarredWalton - Saturday, August 28, 2004 - link

    Not like anyone is going to notice anymore (*wink*), but the article has now been updated with all of the corrections as well as additional commentary. I hope this clarifies a few things. If there are still errors, send them my way!
  • JarredWalton - Friday, August 27, 2004 - link

    Regarding pipeline lengths on Intel products, there are numerous sources that state the P6 core was a 12 stage design. Perhaps the Interger pipeline was shorter and the FP was longer? I don't know for sure, but the majority of information I have read says P6 (PPro, P2, P3, Cel, Cel-2) were all the same core and were all 12 stages. Here's a link to one of the more authoritative CPU information guys that I have read, Jon "Hannibal" Stokes:

    http://arstechnica.com/cpu/004/pentium-1/pentium-1...
    http://arstechnica.com/cpu/004/pentium-2/pentium-2...

    Those contain a histort of the Pentium architecture. Unless you can provide a more definitive source for pipeline lengths, I tend to believe Hannibal. I also heard at the time the original P4 launched that it had "as few as 20 and as many as 28 stages, depending on the instruction being executed and other factors." Something like that. Most people stuck with the "20 stage" figure, but it has become increasingly clear that it was not a straight 20-stage design.
  • IntelUser2000 - Friday, August 27, 2004 - link

    Another correction: the article states 12-stage pipeline for P6 cores? No, its 10, I don't know why some people say P6 cores and its related processors have 12 stage pipelines(exception being PM, because they ARE a different architecture, just not radical as P4), when its 10!!!
  • IntelUser2000 - Friday, August 27, 2004 - link

    First, some corrections.

    mostlyprudent, P4 Willamette is only available up to 2000. They are actually available from 1300-2000. Over 2000 is Northwood cores, which have 512KB L2 cache and is 0.13 micron process.

    Second, why don't anybody seem to notice the pipeline numbers for Prescott on Page 6?

    "The Prescott further extended the NetBurst pipeline to 23 stages in addition to the 8 fetch/decode stages. For whatever reason, Intel generally describes the pipeline of the Prescott as 31 stages while only calling the earlier design a 20 stage pipeline."

    What the hell? Is it actually true? Can the writer, Jarred Walton, please answer this question? Did you just get the facts wrong or is it true that Prescott does have 23 stage pipelines?
  • FlameDeer - Tuesday, August 24, 2004 - link

    Thanks Jarred, very good article! Very useful and helpful processor performance comparison, much better than Intel "BMW" naming! :)

    Some small correction at page 3 Intel Cheat Sheet table:
    Entry no.3 Mendocino is 250nm, 154mm2 only
    Entry no.7 Deschutes Bus Speed is 66 MHz
  • JarredWalton - Tuesday, August 24, 2004 - link

    #36 - I suppose I should have been consistent with the bus speeds. Intel's really is quad-pumped and AMD's really is double pumped. Somehow along the way I redid the Intel side to have the quad pumped bus speed and I didn't redo the AMD side. The Netburst architecture likely benefits a little more from the increased bus speed, but if AMD certainly benefits as well. I'll include that in my updated version later this week. (My left wrist needs a rest. I don't want to risk carpal tunnel syndrome.)

    On the HyperTransport side of things, I really don't regard the HT bus speed as being that important. The old style bus (Athlon Socket A) was a 64-bit 400 MHz bus (200 MHz double-pumped - at least on the 3200+) while HyperTransport is a 16-bit 800 MHz bus. I think that's right, anyway. So 16-bit * 800 MHz (bidirectional) is the same as 400 MHz * 400 MHz (unidirectional). Bleh. Whatever the case, I'm pretty sure the HT bus doesn't really make for the A64 being faster. It helps out tremendously in the Opteron with multiple processors, but that's different.
  • johnsonx - Tuesday, August 24, 2004 - link

    to #38

    There are two Thoroughbred B AXP 2600's. 133/266FSB @ 2133 Mhz (multiplier 15), and 166/333FSB at 2083Mhz (multiplier 12.5). Yours sounds like a 166/333FSB model.

  • mrmorris - Tuesday, August 24, 2004 - link

    #15
    My 2600+ AMD XP runs 2083MHz and its Thoroughbred-B!
  • magratton - Monday, August 23, 2004 - link

    #34 - Sweet. The article made me remember all those years, and that post gave me a great chuckle. Peace! Being an avid comments reader (though not so much a contributor) it is good to finally put a name to a.. well.. a name. Peace!
  • mlittl3 - Monday, August 23, 2004 - link

    Jarred

    Don't mean to be persistent but I was wondering what your thoughts about the bus speed listings were.

    Should AMD Athlon processors be listed with bus speeds like 100, 133, 166, 200 MHz or should it be 200, 266, 333, 400 MHz? Likewise for the AMD Athlon 64, FX, Opteron. They use hypertransport running anywhere from 600 to 1000 MHz and don't advertise a bus speed since the memory controller is integrated (even though everyone knows its 200 MHz X multiplier).

    If the current listed speeds are the way it should be written, what about the Intel bus speeds of 400, 533, 800 and 1066 MHz? These really are 100, 133, 200 and 266 MHz when calculating the actual processor speed.

    Do the Intel quad speed bus speeds really reflect the actual bus speed wherease the AMD double bus speed do not?

    Just wanted to be clear. Thanks. Can't wait for the GPU cheat sheet.

    Mark
  • JarredWalton - Monday, August 23, 2004 - link

    Umm... crap, sort of let the cat out of the bag there. If the "JW" at the end of the other name didn't clue you in, it should be blatantly obvious who I am now. (Although only people that read the news and article comments are likely to have seen the name.)
  • TrogdorJW - Monday, August 23, 2004 - link

    No problem, Dave - I'm not offended by any means. It's "distributed research" as far as I'm concerned. It's SMP for writers (as long as they're computer geeks, at least).

    I of course have only personally dealt with a small fraction of the total number of CPUs, since I have never worked for AMD or Intel. I'm sure there are some employees from those two companies that could provide many missing details if they chose to do so. I have to be honest that I reached the point where I just wasn't seeing any mistakes or ommissions because I had been looking at the charts and data for far too long.

    At some point in the coming months, I may look at addressing some of the remaining gaps (i.e. no P3, P2, Duron, or early Athlon CPUs are listed). Until then, I'll simply work on updating the current charts.

    One final note: I'm amazed (shocked, even) that there hasn't even been one flame about my terrible Shakespeare parody in the introduction. I did it sort of as a joke, but when my wife looked at it, she groaned in pain. You can thank Kris for removing the Timbuk-3 quote from the conclusion. Hahaha... :D

    I've got a busy night (elsewhere), so you'll probably have to wait until after 1 AM PST before I get any real updates to the pages done.
  • KristopherKubicki - Monday, August 23, 2004 - link

    The mobile athlons are better refered to as Mobile Athlon 4,

    Kristopher
  • johnsonx - Monday, August 23, 2004 - link

    Jarred,

    I totally agree with your 'aside note'. I hope you didn't take my corrections/addendums as criticism of your effort; if there is to be a 'CPU Cheatsheet', it should be as correct as possible which takes outside input.

    BTW, I kept my comments to the desktop/server arena because notebooks often use otherwise unknown variants of chips. If mobile chips are included here, then they should be listed as such. For example, it is true that 133/266 FSB Bartons do exist as Mobile AthlonXP's (and the AthlonMP 2800+ as well), but not as regular AthlonXP's. I've seen other odd variants in notebooks; probably chips meant to satisfy a particular OEM's requirements (like I could swear I've seen a notebook with Mobile AthlonXP 1000+). Then of course if you get into Mobile AXP's, then you've got that tiny uPGA socket-563 to deal with as well. What a mess...

    Regarding the 512k Clawhammer vs. Newcastle: I've now gotten the impression that the original OEM 2800+ was (and maybe still is) a Clawhammer, while all the retail ones are Newcastle. My evidence for this theory is that all 3000+ chips are 2.0Ghz, 512k cache; the original ones were 512k Clawhammers and in retail carried the part number ADA3000BOX. The newer ones are Newcastles, and carry the retail part number ADA3000AXBOX. However, the retail 2800+, which came out well after the OEM 2800+, did and still does carry the part number ADA2800BOX. This leads me to conclude that AMD adds the 'AX' when they change cores in the same model number, and further that the retail 2800+ started with the Newcastle core, as the AX has not been added to denote a core change (since I think we all agree that the retail 2800's you can buy today are indeed Newcastles).

    Regards,

    Dave
  • silentsnow - Monday, August 23, 2004 - link

    #25, #26

    There is a general consensus that all 4AP and 4AR OPN's are 512K ClawHammers. All Rev CG 512KB Athlon's are therefore Newcastle based.
  • JarredWalton - Monday, August 23, 2004 - link

    The pipeline stages for Opteron and A64 are indeed 12/17 - that has been corrected, thanks! I had heard that before, but there were quite a few sites that listed it as 10/15 still. I'll have to wait on the other bits (slightly incorrect MHz ranges) until I have a bit more time to spare.

    25/26: Yes, there is a socket 754 Newcastle now. AMD is being a little unclear on a lot of the updates, but apparently they can switch the memory controller quite easily in the core, or else the original memory controller was fully capable of dual-channel support but they somehow just turned it off. Anyway, the original 2800+ and 3000+ chips that showed up were, in all likelihood, downgraded Claw Hammer cores.

    As an aside note, the power of the Internet is rather impressive. It took a whole lot of time (as I'm sure most of you are aware) to research all the data for this article. Of course, there are bound to be mistakes (as JohnsonX and others have pointed out), but the chance of finding those alone is slim to none. It's like writing a modern software application that doesn't have any bugs! Throw something out on the Internet, however, and with thousands of eyes looking at it, your mistakes are sure to be found. :)

    I'll work on verifying and correcting some of the more greivous errors/omissions in the coming day or two. Of course, I'm also working on that little GPU chart... just don't expect die sizes or transistor counts on the chips, as they're very difficult to find. (Not so much the transistor counts, though.)
  • NinjaPirate - Monday, August 23, 2004 - link

    On the Intel Cheat Sheet, the Coppermine Celerons are marked as SMP capable, but it is the Mendocino Celerons who are SMP capable. As far as I know, nobody could get Celeron II to run SMP. Anyway, it's a very good article.
  • AkumaX - Monday, August 23, 2004 - link

    4. There were no 133Mhz FSB AthlonXP Bartons.

    Note that my comments are confined to the desktop arena. The mobile arena tends to get alot more odd variants.

    hehe, trying to keep it to the desktop, i see

    also, the Sempron seems to come in Tbred B and Thorton, and the lowest Sempron i've seen is a 2200+ (1.5ghz @ 166mhz fsb)
  • wassup4u2 - Monday, August 23, 2004 - link

    I was under the impression that the K7 had a 10-stage int pipeline and a 15 stage fp pipeline, and the one of the changes worked in the K8 was an increase to 12/17 stages, effective starting with the first K8 chip, Sledge Hammer.
  • LocutusX - Monday, August 23, 2004 - link

    #25:

    "8. The 512k Clawhammer core was only sold at 2.0 and 2.2Ghz. The 1.8 and 2.4's were true Newcastles right from the start. (ok, this one I'm less than 100% sure of, but I think I'm correct)."

    You're 98% right, I believe. The 512k Claw was only sold @ 2.0ghz, and were the "defective" 3200's remarked as 3000+. These were the ones being reviewed around December/January. Most of the new 3000+'s being sold *today*, are of course "true Newcastle". -- AFAIK!

  • johnsonx - Monday, August 23, 2004 - link

    Perhaps these are ticky-tack, but if you want it to be correct:

    1. The AthlonXP Palomino was never sold at speeds below 1333Mhz (AthlonXP 1500+).

    2. The AthlonMP Palomino was never sold at speeds below 1200Mhz (AthlonMP 1200).

    3. The Thoroughbred 'A' core never reached a speed above 1833Mhz (AthlonXP 2200+). To break beyond that, AMD had to switch to the 'B' core.

    4. There were no 133Mhz FSB AthlonXP Bartons.

    5. The AthlonMP Barton had an FSB of 133, not 166. The only MP chipset, the AMD 760MP/MPX, can only do 133 FSB.

    6. The Thoroughbred 'B' core used for the Semprons is the exact same as those used for AthlonXP's, and thus has the same die size, 84mm^2.

    7. The Socket-939 AthlonFX is a ClawHammer, not a SledgeHammer. The 'Sledge' requires Registered memory and socket-940.

    8. The 512k Clawhammer core was only sold at 2.0 and 2.2Ghz. The 1.8 and 2.4's were true Newcastles right from the start. (ok, this one I'm less than 100% sure of, but I think I'm correct).

    9. You left out the Socket-754 variant of the NewCastle. The Newcastle core starts at 1.8Ghz (S754 2800+), and so far goes up to 2.4Ghz (S754-3400+ and S939-3800+).

    Note that my comments are confined to the desktop arena. The mobile arena tends to get alot more odd variants.
  • mlittl3 - Monday, August 23, 2004 - link

    I have one problem with this article.

    The bus speeds for all AMD processors are given at their actual bus speed (100, 133, 166, etc.) instead of double the speed as given by marketers. That way, when you multiply the bus speed by the multiplier in the next column, you get the right overall speed of the processor.

    However, the bus speeds for alll Intel processors are listed as their marketing bus speeds (400, 533, 800, etc.). When you multiply this number by the multiplier in the next column, you get four times the actual overall speed (the 3.80 Ghz would be calculated as 15.2 Ghz and I don't think Intel could cool that processor very well).

    Why do Intel processors have their bus speeds listed by their quad-pumped rating and the AMD processors don't have the "DDR" rating of their bus speeds?

    Other than a few typos, great article.
  • ThelvynD - Monday, August 23, 2004 - link

    You don't have the Socket 604 1.6Ghz Xeons listed in this article that I'm sure alot of folks bought from this thread. http://forums.anandtech.com/messageview.cfm?catid=...
  • LocutusX - Monday, August 23, 2004 - link

    Also, doesn't the A64's ALU have a 12-stage pipeline already?
  • LocutusX - Monday, August 23, 2004 - link

    No Socket 754 Newcastle? Then what the heck's in my computer? ;)

    (not to mention, "what the heck were those earlier AT articles about?")
  • mostlyprudent - Monday, August 23, 2004 - link

    The P4 Willamete 478 is listed at 1500-2000 - I believe that should be 2400. I have the 2200!
  • Jalf - Monday, August 23, 2004 - link

    Athlon 64's do have longer pipelines than Athlon XP.
    And a year or so ago, they talked about adding a few more stages (I think it was supposed to be in the Winchester core)
    There's also a lot more to the Athlon 64's good performance than "purely the memory controller".

    Apart from that, cool article. :)
  • appu - Monday, August 23, 2004 - link

    One of the best articles I've ever seen on AT - up there with the likes of the Memory Holy Grail series and such. Amazingly thorough and researched. I just can't wait for the GPU cheat sheet now! You have that coming as well, don't you? Also, as mentioned by Crassus, it'd be really nice to have the quarter of year information in the tables.
  • Myrandex - Monday, August 23, 2004 - link

    Deschutes P II Slot 1 266-333 512K 7.5 + 37.2 250 118 + L2 100 1-2

    that should be 66 and not 100 for FSB. Other than that, sweet article. I think there is an AthlonXP-M for S754 w/ the 64bit disabled, but still has an integrated memory controller and stuff like that. I think Compaq and HP sell notebooks with that.
    Jason
  • Crassus - Monday, August 23, 2004 - link

    Great article. If you happen to have some time more I think it would be nice if you could add the years to the the tables of when each processor was officially sold/produced.
  • Rellik - Monday, August 23, 2004 - link

    The 2600+ AMD XP and MP at 266FSB (Thoroughbred B)
    are 2133 Mhz, not 2083. That is the Speed of the first 333FSB Barton 2600+

    Nitpickmode off :-)
  • Anemone - Monday, August 23, 2004 - link

    Isn't the Athlon 64 3700 the Odessa or what was supposed to be Odessa in the original code names?

    Just checking, love this article sorting through all the would be's and once were's, back in time.
  • JarredWalton - Monday, August 23, 2004 - link

    plewis - Rosewood is correct in stating that *all* Athlon 64 processors have an integrated memory controller. That means that all S754, S939, and S940 motherboards do not have a memory controller, so any other chips made for those boards (i.e. Sempron 3100+) also have to have an integrated memory controller. I believe there are some benchmarks on AT that show how the 1.8 GHz Sempron 3100+ compares to the Athlon XP chips. Basically, it beats them in almost all cases.

    Rosewood - Regarding the 250 nm 233-333 processors, they definitely existed in at least a couple of the processors, late in the PII lifetime. I personally purchased a Pentium II 300 batch SL2W8 - there was a big deal made over many of these being downmarked PII 450 chips at the time. It overclocked to 450 MHz like a champ! :)

    How many of these were made? I don't think there were very many. After all, it wasn't too long after the introduction of the 100 MHz bus PII chips that the 66 MHz bus chips were discontinued by Intel. (At least, that's how I remember it.) However, I don't know if they only released 250 nm versions inthe 300 and 333 models, or if they were also in some 233 and 266 models. I do know that *some* of the chips at least exist.
  • rosewood - Monday, August 23, 2004 - link

    plewis00 - unless im on crack, I think all the A64s have had the memory controller on chip and not on the NB, including the 754s.
  • plewis00 - Monday, August 23, 2004 - link

    Can I ask, I am not that well informed on AMD processors, but if the Sempron 3100+ is an S754 chip, then how can it have an integrated memory controller, because I thought on all S754 boards, the memory controller is in the Northbridge? Am I right?
  • rosewood - Monday, August 23, 2004 - link

    Great article - good history. Two things

    Klamath P II Slot 1 233-333 512K 7.5 + 37.2 350/250 203 + L2 66

    Are we sure that there were 250 parts of this line? I beleive ya but a bro says thats not right so ... yea?

    2)
    Can you include the A64 Mobiles as they are a bit different. IIRC, I have a 3000+ in my laptop and its 1.8ghz but 1meg L2 Cache.

    3) I said two? Well, I just thought of this one :P Could you add pictures of the stuff if possible as well as model # guides / how to tell. I was recently given a tray of CPUs and if I try I can probably noodle through which is which but it would be nice to just look here and say "Ah yes, this 2200+ is a barton because the core looks like this ..."

    But seriously, AWESOME article.
  • Holobits - Monday, August 23, 2004 - link

    Good Job Jarred!! Reading your article started bringing me back memory of my pentium 2 and 2 3dFX Voodoo 2s in SLI:) Your article is very informative and I look forward to seeing another.
  • JarredWalton - Monday, August 23, 2004 - link

    srg - They're with the Pentium 3 and early Celeron processors. :) If people are really interested in getting the list of Slot A and Slot 1 processors for AMD and Intel, I can work on compiling that. Initially, I just felt they were old enough that it wasn't worth the effort.
  • MAME - Monday, August 23, 2004 - link

    ha, whoops

    anyway, nice article!
  • MAME - Monday, August 23, 2004 - link

  • srg - Monday, August 23, 2004 - link

    What about the Slot A Thunderbirds? OK, their basically 'B' types but still.

    srg
  • JarredWalton - Monday, August 23, 2004 - link

    There were some difficulties with the initial tables due to the way I wrote the HTML and the posting engine. Sorry for anyone that saw the "corrupted" tables. With the decreased font size, they should look a little better now.
  • TrogdorJW - Monday, August 23, 2004 - link

    They are, Pumpkin. That's how it's showing up as well. Only the forthcoming P4EE 3.73 GHz will be something else, AFAIK. It's listed as a Prescott with 2 MB L2 cache.
  • Pumpkinierre - Monday, August 23, 2004 - link

    I thought P4EEs were Gallatin cores. It seems to correspond to the 2MB L3 Gallatine cored Xeon in description.
  • Maleficus - Monday, August 23, 2004 - link

    Very well written, very informative. Excellent job!

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